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AOZ1977
Pin Functions
T AUTORESTART = ---------------------------
R OSC ? ? 10 pF
Pin 1: VIN
This is the input power for the controller IC. If the input of
the boost converter is less than 30 V, VIN can be
connected directly to the boost supply voltage. If the
boost supply voltage is higher than 30 V, a separate
supply rail between 8 V to 30 V is required for the
VIN pin. It is recommended that an RC filter is added
between VIN and the boost supply voltage if they are
connected directly.
Please note that when VIN is not directly connected to
the boost supply voltage, proper power up sequence will
be required. Boost supply voltage must be ready before
powering up VIN. There is no power down sequence
required.
Pin 2: VDD
This is the output of an internal 8 V regulator. It requires a
2.2 ? F decoupling capacitor to be connected to ground.
The internal regulator can be over-driven by an external
supply between 8 V to 16 V if higher gate drive is desired.
PIN3: GATE
This is the driver output for the gate of the boost NMOS
switch. The GATE = high voltage is equal to VDD
voltage. It is recommended to add a 1 ?? resistor between
this pin and the NMOS gate. The resistor value can be
optimized depending on the switching frequency and
selection of the NMOS switch.
PIN 4: GND
This is the signal and power ground for the IC controller.
It is recommended that all the low current paths are
connected to this pin as close as possible to the IC
controller. It is not recommended to connect any output
or input filter capacitors and any current sense resistors
to this pin directly. The IC controller ground should be an
island around the IC connected to the PWR GND at a
single point in the layout.
PIN 5: CS
This is the input for peak current sense. This pin serves
the functions of current feedback, peak current limit
detection, and fault current detection. The pin current
limit is set by the voltage defined at PIN 9 ILIM. The
current limit is defined as voltage at ILIM divided by the
sense resistor connected from this pin to ground.
If the CS pin detect a fault current detection such as short
circuit condition, it will trigger a fault signal. The IC
controller sets to either latch-off mode or auto restart
mode depends on the setting at PIN 6 AUTO.
PIN 6: AUTO
This is the mode control for fault condition. The selection
of control when under fault condition is either auto restart
mode or latch-off mode. For latch-off mode, this pin
should be connected directly to ground. For auto restart
mode, this pin should connect a capacitor to ground. The
auto restart period will be determined by the following
equation:
C ? AUTO ?
1.25 uA
PIN 7: OSC
OSC is the pin to select the switching frequency for the
boost controller. A resistor should be connected between
this pin to ground. The switching frequency is determined
by the following equation:
1
F SW = -----------------------------------------
It is recommended that the switching frequency for
normal operation is between 50 kHz to 350 kHz.
Pin 8: SYNC
This is a bidirectional pin for oscillator clock
synchronization. Clock synchronization will choose either
the internal clock or the external clock through this pin,
whichever is faster. The faster external clock must be
ready before power is applied to this IC controller. If the
internal clock is faster, the SYNC pin will have the same
frequency as the internal clock. When multiple IC
controllers are used in the design, it is recommended to
connect all SYNC pins together. This will reduce the
interference of “beat” frequencies associated with
multiple switching frequencies.
PIN 9: ILIM
This is the current limit set point. The voltage at this pin
will determine the CS current limit threshold detected at
PIN 5: CS. The voltage can be derived from a resistor
divider from the 1.2 V reference voltage at PIN 10: VREF.
To minimize power consumption, it is recommended that
the total resistance for the divider is approximately 20 k ? .
PIN 10: VREF
This is a 1.2 V voltage reference for all external bias.
This reference voltage can be used for PIN 15: ISET and
PIN 9: ILIM bias.
Rev. 2.1 May 2012
www.aosmd.com
Page 3 of 16
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